There is a continuous effort in the semiconductor industry directed toward increasing device density by scaling down the feature sizes of the MOS transistors which are formed in the device. When such scaling occurs, the depths of the source and drain regions must be reduced proportionally. This, however, increases the resistivity of those N.sup.+ and P.sup.+ diffusion regions thereby decreasing the speed of the MOS integrated circuit. Further, very shallow source and drain regions are susceptible to metal spike through from the metallization at the contact areas of the N.sup.+ and P.sup.+ regions.
One structure for overcoming some of these problems is disclosed in U.S. Pat. No. 4,384,301 which issued May 17, 1983 to Tasch, Jr. et al. Tasch discloses an MOS field effect transistor for an integrated circuit having metal silicide regions in the source, drain, and gate where ohmic contact is made with the integrated circuit metallization. Metal silicide effectively reduces the incidence of metal spike through into the source and drain regions by preventing aluminum diffusion through the silicide. When forming metal silicide contact areas on the source and drain regions, one must be certain to prevent the metal silicide from extending to the gate thereby shorting the transistor. Tasch accomplishes this by depositing a layer of silicon dioxide over the entire device, subjecting the layer to an argon implant which is perpendicular to the surface of the device, then, using a hydrofluoric acid etch, removing the implanted areas of the deposited oxide layer. This leaves a layer of silicon oxide only on the vertical sidewalls of the gate. When the metal silicide is formed on the source and drain regions, the oxide on the sidewalls of the gate prevents contact between the gate and the metal silicide. With this process, however, the argon implant represents an extra processing step that is not easily incorporated into existing wafer fabrication lines.
Tasch forms the metal silicide in a three step process beginning with sputtering platinum on the entire surface of the wafer. The wafer is then annealed to form platinum silicide areas on the source and drain regions. Platinum which was not converted to platinum silicide is then selectively removed by means of an aqua regia etch. Here again, an extra processing step is introduced by the necessity of etching away unwanted platinum.
These extra steps, which add complexity to the manufacturing process, necessarily increase the cost of manufacturing and ultimately can affect yield. What is desired is a manufacturing process for making integrated circuit devices having MOS field effect transistors with metal silicide contact areas on the source, drain, and gate, which is both efficient and reliable.